1. Field of the Invention
This invention relates to computer design, and particularly to a hierarchical organization of arrays in a computer allowing creation of translation caches permitting maintaining the coherency of the entries in hierarchical computer tables without impacting service time of requests of the tables or requiring excessive space or logic.
2. Background of the Invention
In computers, the design of dynamic high-speed access tables (arrays), such as translation caches, can often be enhanced through a hierarchical (multi-level) organization, as opposed to a flat (single-level) organization. A multi-level scheme features entries that are associated with a particular level, perhaps in different tables, with each lower-level entry associated with a particular higher-level entry. The intent of the higher-level (parent) entries is that they share information common to all of their corresponding lower-level (child) entries. This not only saves space (chip area is probably the most important component of microprocessor design), it allows many common functions to be performed on a single parent entry instead of numerous child entries, which can improve performance and simplify the design.